description the CXD1170M is a 6-bit 40mhz high speed d/a converter. the adoption of a current output system reduces power consumption to 80mw (200 load at 2vp-p output). this ic is suitable for digital tv and graphic display applications. features resolution 6-bit max. conversion speed 40msps non linearity error within 0.1lsb low glitch noise ttl cmos compatible input +5v single power supply low power consumption 80mw (200 load at 2vp-p output) block diagram and pin configuration structure silicon gate cmos ic function 6-bit 40mhz d/a converter ?1 CXD1170M e89x37b6x-ps 6-bit 40msps high speed d/a converter sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 24 pin sop (plastic) current cells latches decoder dv dd io io vg dv dd av dd vref 19 20 21 22 23 24 clock generator nc nc (lsb) d0 d1 d2 d3 d4 d5 blk dv ss vb clk 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 current cells (for full scale) bias voltage generator dv ss iref decoder av ss av dd av dd
?2 CXD1170M absolute maximum ratings (ta = 25?) supply voltage v dd 7v input voltage v in v dd to v ss v output current i out 15 ma storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 4.75 to 5.25 v dv dd , dv ss 4.75 to 5.25 v reference input voltage v ref 2.0 v clock pulse width tpw 1 12.5 (min) ns tpw 0 12.5 (min) ns operating temperature topr ?0 to +75 ? pin description and i/o pins equivalent circuit no. symbol equivalent circuit description 10, 13 dv ss digital gnd 14 av ss analog gnd 3 to 8 d0 to d5 digital input 9 blk blanking pin no signal at "h" (output 0v) output condition at "l" 11 vb connect a capacitor of about 0.1 f 12 clk clock pin moreover all input pins are ttl-cmos compatible dv dd dv ss to 3 8 dv dd dv ss 9 dv dd dv ss dv dd 11 dv dd dv ss 12
?3 CXD1170M no. symbol equivalent circuit description 15 iref connect a resistance 16 times "16r" that of output resistance value "r" 16 vref set full scale output value 17 vg connect a capacitor of about 0.1 f 20 io current output pin voltage output can be obtained by connecting a resistance 21 io inverted current output pin normally dropped to analog gnd 23, 24 dv dd digital v dd 18, 19, 22 av dd analog v dd av ss av ss av dd av dd av ss av dd av dd 15 16 17 av dd av ss av dd av ss 20 21 eleoctrical characteristics (f clk = 40mhz, v dd = 5v, r out = 200 , v ref = 2.0v, ta = 25?) item resolution maximum conversion speed minimum conversion speed linearity error differential linear error full scale output voltage full scale output current offset output voltage power supply current digital input current setup time hold time propagation delay time glitch energy measurement conditions 14.3mhz, at color bar data input r out = 75 min. 0.5 ?.3 ?.1 1.85 13 ? 5 10 typ. 6 1.95 10 14.5 10 30 max. 40 0.5 0.1 2.05 15 1 16 5 unit bit msps mhz lsb lsb v ma mv ma ? ? ns ns ns pv-s symbol n f max f min e l e d v fs i fs v os i dd i ih i il t s t h t pd ge high level low level
?4 CXD1170M maximum conversion speed test circuit clk 40mh z square wave clk 0.1 200 oscilloscope blk vb io vg vref iref 1k avss 0.1 3.3k av dd 3 4 8 9 11 12 15 16 17 20 d5 d0 (lsb) 6bit counter with latch 2v dc characteristics test circuit clk 40mh z square wave clk 0.1 200 blk vb io vg vref iref 1k avss 0.1 3.3k av dd 3 4 8 9 11 12 15 16 17 20 d5 d0 (lsb) dvm 2v controller propagation delay time test circuit clk 10mh z square wave clk 0.1 200 oscilloscope blk vb io vg vref iref 1k avss 0.1 3.3k av dd 3 4 8 9 11 12 15 16 17 20 d5 d0 (lsb) frequency demultiplier setup hold time and glitch energy test circuit clk 1mh z square wave clk 0.1 75 oscilloscope blk vb io vg vref iref 1k avss 0.1 1.2k av dd 3 4 8 9 11 12 15 16 17 20 d5 d0 (lsb) 6bit counter with latch 1v delay controller delay controller
?5 CXD1170M operation timing chart t pw1 t pw0 clk aaa aaa aaa aa aa aa aa aa aa aa aa aa t s t h t s t h t s t h data t pd d/a out 50% 100% 0% t pd t pd application circuit dv dd (lsb) av dd 200 0.1 2v 0.1 1k 3.3k dgnd d/a out agnd 19 20 21 22 23 24 13 14 15 16 17 18 6bit digital input 2 3 4 5 6 7 8 9 10 11 12 1 i/o chart (when full scale output voltage at 2.00v) input code msb lsb 1 1 1 1 1 1 : 1 0 0 0 0 0 : 0 0 0 0 0 0 output voltage 2.0v 1.0v 0v application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?6 CXD1170M notes on operation how to select the output resistance the CXD1170M is a d/a converter of the current output type. to obtain the output voltage connect the resistance to io pin. for specifications we have: output full scale voltage v fs = less than 2.0 [v] output full scale current i fs = less than 15 [ma] calculate the output resistance value from the relation of v fs = i fs r. also, 16 times resistance of the output resistance is connected to reference current pin i ref . in some cases, however, this turns out to be a value that does not actually exist. in such a case a value close to it can be used as a substitute. here please note that v fs becomes v fs = v ref 16r/r'. r is the resistance connected to io while r' is connected to i ref . increasing the resistance value can curb power consumption. on the other hand glitch energy and data settling time will inversely increase. set the most suitable value according to the desired application. phase relation between data and clock to obtain the expected performance as a d/a converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. be sure to satisfy the provisions of the setup time ( t s ) and hold time ( t h ) as stipulated in the electrical characteristics. v dd , v ss to reduce noise effects separate analog and digital systems in the device periphery. for v dd pins, both digital and analog, bypass respective gnds by using a ceramic capacitor of about 0.1 f, as close as possible to the pin. latch up av dd and dv dd have to be common at the pcb power supply source. this is to prevent latch up due to voltage difference between av dd and dv dd pins when power supply is turned on.
?7 CXD1170M 1.0 0 1.0 2.0 output full scale voltage vs. reference voltage v ref ?reference voltage [v] v fs ?output scale voltage [v] v dd = 5.0v r = 200 w 16r = 3.3k w ta = 25? 2.0 0255075 ?5 0 v dd = 5.0v v ref = 2.0v r = 200 w 16r = 3.3k w ta = 25? output full scale voltage [v] 1.9 2.0 output full scale voltage vs. ambient temperature ambient temperature [?] 100 100 output resistance vs. glitch energy output resistance [ w ] glitch energy [pv-s] 200 200
?8 CXD1170M package outline unit: mm sony code eiaj code jedec code m package structure molding compound lead treatment lead material package weight epoxy/phenol resin solder plating copper alloy / 42alloy 24pin sop (plastic) 15.0 ?0.1 + 0.4 112 13 24 1.27 0.45 0.1 5.3 ?0.1 + 0.3 7.9 0.4 0.2 ?0.05 + 0.1 0.5 0.2 0.1 ?0.05 + 0.2 0.15 1.85 ?0.15 + 0.4 6.9 0.12 sop-24p-l01 * sop024-p-0300-a 0.3g
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